1. Field of the Invention
This invention is concerned with a method for verifying the architectural integrity of a processor having only a limited or partial instruction set. More particularly, this invention is directed to a methodology for performing such verification on a minimal instruction set or on single instructions to control and then cause execution thereof and to then capture the results of execution.
2. Description of the Prior Art
It is well known that a newly written or significantly modified instruction set for a given processor needs to be tested and proper execution thereof verified before that set can be relied on. Traditionally, software written to verify the operating architectural integrity of such an instruction set has been written as comprehensive programs that were resident in the processor under test. This approach requires a rather complete implementation of the instruction set and an operational input/output (I/O) facility before serious testing can and does begin.
Instructions have been tested in the past on an individual basis, but such testing requires one to employ hand loops that are manually entered, generally via an operator's console. It was found, however, that the number of different drivers which resulted from the many microcode test efforts, made it difficult to standardize such testing or trust its results, even where testing different code portions of the same instruction set. In addition, this non-automated manual entry verification approach was subject to frequent non-microcode error entry and was, therefore, not conducive to efficient testing.
Thus, the prior art relating to architectural verification and/or diagnostics is primarily concerned with automated and semi-automated means and methods for discovering microcode or hardware problems after the complete instruction set and I/O routines have been written. Debugging is generally a piecemeal effort that is serial in nature, discovery of a first bug leading to discovery of related or subsequent bugs, requiring large test driver programs to exhaust all possibilities. Commonly assigned U.S. Pat. No. 4,268,902 to Berglund et al and U.S. Pat. No. 4,312,066 to Bantz et al are typical of such prior art approaches. These patents are both directed to diagnostic and debug methods in which a service or diagnostic processor is attached to a fully operational host having a complete instruction set and full I/O capability to test or diagnose the instruction set or to find the cause of a particular host error. Similar approaches are detailed in commonly assigned U.S. Pat. No. 3,618,028 to Johnson et al and U.S. Pat. No. 3,825,901 to Golnek et al.
Unfortunately, utilization of these prior art methods required that operational verification of a new or substantially modified instruction set be held in abeyance until the set was completed and full I/O capability provided. In addition, errors made during the development stage, particularly during the early portion thereof, were often propagated through the entire development effort and not found until that effort was completed and verification testing performed. This meant that additional time had to be spent correcting or rewriting all of the code that contained such propagated errors rather than merely correcting an erroneous instruction.